Laser fault emulator : free fault injection platform on Virtex5 boards

The main goal of task T4-ST3 was to make available a fault injection platform based on emulation on a FPGA platform. The advantage of such a platform is the possibility of more extensive fault injection campaigns compared with simulated fault injections, due to the ratio in terms of execution time (typically several orders of magnitude). In order to reduce the time required by the set-up of the emulation, it is however necessary to have a generic environment, helping the designer in setting up his own experiments. The work started from a previous version of the platform available at TIMA. Several improvements were worked out in the context of LIESSE. At that time, the platform is fully operational on a quite recent and efficient but cheap FPGA (Xilinx Virtex 5) and it has been used for many experiments during the project. A generic environment has been made open-source, as expected, along with documentation (user guide) and a working example. The available environment allows injecting early in the design flow single- or multiple-bit errors according to several fault models, including bit-flip, bit-set, bit-reset and stuck-at. Either exhaustive or statistical fault injection is supported.

For free download: Page/ATE-FIT5.htm